HeyJaredChester Lam
- Indexed articles, last 90 days
- 6
- Latest publication
- Aug 30, 2026
- Outlet visibility, for Chipsandcheese
- Top 5M sites
- Earliest in this view
- Jul 14, 2026
Latest articles
Hot Chips 2026: XCENA and Samsung’s Near-Memory Compute CXL Device (opens the original)
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Memory expansion has been attractive for years, and is more relevant than ever because ML models have an insatiable appetite for memory capacity. In response, XCENA has worked with Samsung to create a CXL memory expansion device that can also host SSDs and do compute. The device is called MX1, where MX stands for “Memory Xcelerator”. On the memory expansion front, the MX1 can host up to 2 TB of DDR5 memory and connects to the host via a PCIe 6/CXL 3.2 x8 interface. The MX1 therefore has 128 GB/s
Hot Chips 2026: Samsung’s Processing-in-Memory (PIM) (opens the original)
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In-memory compute has been an attractive proposition for many years because compute within a memory chip can exploit its higher internal bandwidth. Additionally, in-memory compute avoids the long latency path between DRAM and traditional compute cores. At Hot Chips 2026, Samsung discusses their continued pursuit of in-memory compute with their PIM (Processing-in-Memory) push. They’re implementing MAC units within LPDDR5X chips, while preserving the chip’s ability to interface with a standard mem
Hot Chips 2026: CUDA Targets RISC-V (opens the original)
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CUDA is a giant for GPU compute, which includes machine learning applications. So far, CUDA supports x86-64 and aarch64 CPUs. Now, Nvidia is looking at extending CUDA support to RISC-V. This move opens the door for RISC-V CPUs to feed GPU compute. Nvidia’s talk focuses on the requirements that RISC-V CPUs must fulfill to work with CUDA. Basically, they want a server-grade CPU and platform. Nvidia starts by requiring a RVA23 CPU, and adherence to RISC-V’s server SoC and server platform specificat
Hot Chips 2026: Applying High Bandwidth Flash (HBF) (opens the original)
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HBF, or High Bandwidth Flash, uses the same flash memory technology we see in SSDs today. Unlike SSDs, HBF is implemented much like HBM (High Bandwidth Memory). HBF cubes sit on the same package as a compute chip, perhaps even next to HBM. HBF’s idea is to offer much higher capacity than HBM, while still providing decent memory bandwidth. At Hot Chips 2026 tutorials day, Anurag Agarwal and Radhakrishna Giduthuri’s talk explores how HBF could apply to machine learning workloads. No HBF products e
Hot Chips 2026: Samsung and HBM Base Die Opportunities (opens the original)
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HBM, or High Bandwidth Memory, stacks multiple DRAM dies on top of a base die. The dies interface with each other via TSVs, while the base die talks with whatever compute die is using the memory via an interposer. Increasing bandwidth for a new HBM generation involves scaling up bandwidth between the DRAM dies and the base die, as well as scaling bandwidth from the base die to the host. Denser TSVs and more TSVs can easily achieve the former. The latter is more challenging, because the physical
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