HeyJaredHow Tech - Systems Programming
Build Real Systems, Not Toy Projects This isn't another course with abstract diagrams and theoretical discussions. You'll write code, debug performance problems, and optimize real systems under realistic load patterns.
- Indexed issues, last 90 days
- 17
- Latest publication
- Sep 30, 2026
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- Aug 22, 2026
Latest issues
Hardware Acceleration and Heterogeneous Compute: Building and Debugging a Rust Driver for RISC-V Architecture (opens the original)
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1. IntroductionHeterogeneous compute is no longer a datacenter novelty. Every modern SoC — from a RISC-V-based edge camera to a multi-tile AI accelerator card — pairs a general-purpose CPU cluster with one or more special-purpose compute engines: NPUs, DSPs, cryptographic offload blocks, or vector coprocessors. The kernel’s job is to expose these engines to userspace safely, cheaply, and predictably, without becoming the bottleneck it’s meant to eliminate.This lesson builds a real memory-mapped
Debugging RISC-V Firmware with GDB and OpenOCD: From JTAG Signal to Source-Level Breakpoint (opens the original)
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1. IntroductionDebugging firmware is fundamentally different from debugging a userspace process. There is no ptrace(), no scheduler to preempt into a debugger, and frequently no operating system at all — just a hart sitting at its reset vector, executing whatever is in flash or ROM. On RISC-V, the mechanism that makes this possible is not a proprietary vendor protocol but an open, ratified specification: the RISC-V External Debug Support spec, which defines a hardware Debug Module (DM) inside th
Issue 06 — Ingestion Pipeline: Kafka to ClickHouse (opens the original)
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Issue 05 got events off the host with mTLS. This issue places a streaming broker between ingest and storage so write spikes from hundreds of agents do not couple directly to ClickHouse merges. The consumer projects Phase A OCSF-shaped JSON into columnar rows using docs/ocsf-mapping.md — it does not invent a second field dialect.Broker decoupling and columnar storageAgents burst. A broker (raw.telemetry on Kafka/Redpanda) absorbs those bursts: ingest acknowledges quickly, consumers catch up async
Porting a Linux Distribution to a Custom RISC-V SoC: Hardware Acceleration and Heterogeneous Compute (opens the original)
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1. IntroductionPorting a general-purpose Linux distribution — a tailored Debian, in this case — to a custom RISC-V System-on-Chip is not a single task. It is a sequence of tightly coupled engineering problems that span firmware, bootloaders, kernel configuration, device drivers, toolchains, and package management. Unlike bringing up Linux on an existing reference board (a QEMU virt machine, a SiFive HiFive Unmatched, or a StarFive VisionFive), a custom SoC forces the engineer to confront every l
Low-Power Firmware for RISC-V Cores: Inside the SBI HSM Idle Handshake (opens the original)
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1. IntroductionEvery time a Linux system goes idle — a phone’s screen turns off, a server’s request queue drains, an IoT sensor finishes a sampling cycle — something has to decide how deeply to sleep the CPU, and something has to reliably wake it back up. On x86 that decision lives almost entirely inside the kernel: MWAIT and ACPI C-states are architected instructions and firmware tables the kernel can drive directly. On RISC-V, the story is split across a boundary that trips people up the first
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