HeyJaredCondor Currents
Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community.
- Indexed episodes, last 90 days
- 75
- Latest publication
- Sep 19, 2026
- Audience
- Checking…
- Earliest in this view
- Jul 3, 2026
Latest episodes
PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving (opens the original)
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## Episode Summary In this episode, we cover: - **PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving** (arXiv) - **Understanding and Exploiting Diagonal Attention Sparsity in Autoregressive Image Generation** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Kari Hepola: Custom tools make RISC-V processors faster and easier to design - tuni.fi** (google_riscv) - **Enabling Comprehensive CWE-based Assu
RISC-V and machine learning: a survey (opens the original)
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## Episode Summary In this episode, we cover: - **RISC-V and machine learning: a survey** (arXiv) - **MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators** (arXiv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch) - **nRF54LC10A SoC features Cortex-M33, RISC-V coprocessor, Bluetooth LE, Thread and Zigbee - LinuxGizmos.com** (google_riscv) - **SpacemiT to launch server-class
Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator (opens the original)
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## Episode Summary In this episode, we cover: - **Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator** (arXiv) - **HBFlex: A Flexible Memory System for Bridging Fine-Grained LLM States and Coarse-Grained HBF Parallel Execution** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - nature.com** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv)
The World Model Hardware Accelerator (opens the original)
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## Episode Summary In this episode, we cover: - **The World Model Hardware Accelerator** (arXiv) - **A 25-$μ$s/inf Event-driven Graph Neural Network Processor with Spatiotemporal Caching and Spline Convolution for Ultra-low-latency AI at the Edge** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - chinadaily.com.cn** (google_arch) - **Your Nvidia GPU has
BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference (opens the original)
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## Episode Summary In this episode, we cover: - **BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference** (arXiv) - **Arborist: Algorithm-Hardware Co-Design for Fast and Efficient Motion Planning** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **SiFive RISC-V is an Open-Source Processor! - ServeTheHome** (google_riscv) - **RISC-V Processor Advances Local Chip Design - Open Source F
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